1. Field of the Invention
The present invention relates to a multi-layer interconnecting technique, and in particular to a transfer mark structure for the multi-layer interconnecting process for avoiding the effect of dishing on the formation of a groove-like pattern, and for increasing and stabilizing the reading accuracy of a transfer mark used for transfer in the following step so as to align with the transfer location in the preceding step; and a method for manufacturing such a transfer mark structure for the multi-layer interconnecting process.
2. Description of Related Art
Heretofore, in the manufacture of a semiconductor device using more than one transfer using masks, a transfer mark has been used for performing transfer in the following step so that the resist pattern is aligned to the resist pattern transferred in the previous step. As such a transfer mark, there is a reading mark for alignment by optically reading the pattern with transfer equipment, an alignment inspection mark for detecting misalignment of the resist pattern formed by transfer with the resist pattern formed in the previous step or the like. When a transfer mark is formed in the step of forming a contact hole for interconnecting multiple layers, an interconnecting layer is normally provided on the entire area under the transfer mark.
FIG. 16 shows a top view of an example. FIG. 16 is a top view for illustrating a first prior art transfer mark. Hatched areas are groove patterns 100 formed in the hole forming step of detecting locations in the right-left direction (horizontal direction) in the drawing. Under the groove patterns 100 is formed an underlying layer 102 having an interconnecting layer. Here, the width of the groove patterns 100 is, for example, about 0.5 xcexcm, the repeating pitch of the groove patterns 100 is, for example, about 5-15 xcexcm, and the length of the groove patterns 100 is, for example, about 50-100 xcexcm.
In recent years, however, due to size reduction of electronic devices, it has been required for metal wiring to reduce the thickness of the wire and the distance between the wires to about 0.3 xcexcm or less. The formation of a resist pattern on a metal film using the transfer technique is difficult due to halation caused by the high reflectivity, and a technique known as Damascene is used. The Damascene is a method for first forming groove patterns 100 on an insulation film such as silicon dioxide (SiO2) corresponding to the shape of interconnection, and forming one or more conductive layers on the entire surface, followed by the removal of conductor layers other than the conductor layer in the groove patterns 100 using CMP (Chemical Mechanical Polishing).
Another prior art is, for example, the one disclosed in Japanese Patent Laid-Open No. 10-229085 (second prior art). The objects of the second prior art are to decrease the deterioration of flatness of pad interconnection due to dishing during CMP, and to perform the reliable test of semiconductor elements. The inventions of the second prior art are, a semiconductor device having a pad comprising a wide interconnection provided on the semiconductor device by the Damascene method, or a multi-layer interconnection structure on the interconnection, wherein a slit is provided in the plane region of the interconnection or each interconnection layer of the multi-layer interconnection structure; a semiconductor wafer having a pad comprising a multi-layer interconnection structure used as the probe of the test element group (TEG) of the semiconductor element electrically connected to the interconnection provided on the semiconductor device by the Damascene method, wherein a slit is provided in the plane region of each interconnection layer of the multi-layer interconnection structure; and a method for manufacturing a semiconductor device comprising the step of forming a pad of a multi-layer interconnection structure on the interconnection provided on the semiconductor device by using the Damascene method, further comprising the steps of forming a slit in the plane region of each interconnection layer of the multi-layer interconnection structure before dishing is performed in the Damascene method, and subjecting the structure having the slit formed in the plane region to chemical mechanical polishing for planarizing, and laminating one after the other. In such second prior art, when the pattern of the interconnection portion is wide in the interconnection structure by using the Damascene method, since the area to be polished is decreased in particular by providing a slit in the plane region of the pad used as the probe for TEG, and no depression is formed by the dishing effect, the deterioration of flatness of the pattern of the interconnection portion due to dishing during CMP may be decreased, thereby the flatness of the interconnection may be secured in the pad of the multi-layer interconnection structure by using the Damascene method, even if the pad of the test element group (TEG) for evaluating the quality of the semiconductor element in a uniform interconnection pattern is arranged on a large area as in conventional methods. Therefore, there is disclosed the effect that the test for evaluating the quality of the semiconductor element may be performed reliably.
However, the above-described prior art has the following problems. FIG. 17 is a sectional view of an element structure along the line C-D of FIG. 16 for illustrating dishing, which is a problem in the Damascene method, FIG. 18 is a sectional view of an element structure along the line E-F of FIG. 16 for illustrating dishing, which is a problem in the Damascene method, and FIGS. 19 through 22 are sectional views of an element structure along the line C-D of FIG. 16 for illustrating the problem of dishing. The first problem is that a wide groove pattern 100 (for example, about 50 xcexcm or more) causes a phenomenon that the central portion becomes excessively concave (dishing) as FIGS. 17 and 18 show. The problem of dishing is consecutively shown in FIGS. 19 to 22. First, as FIG. 19 shows, an oxide film 104 in the portion forming the interconnection layer is etched. Next, as FIG. 20 shows, a metal film 106 of a single-layer or multi-layer structure is formed on the surface of the oxide film 104. As FIG. 21 shows, if the portion in the vicinity of the center of the oxide film 104 becomes concave during CMP, the shape of an insulation film layer 108 between interconnections formed thereon reflects a groove pattern 100 (see FIG. 22). If the mark for the hole forming step is formed on this insulation film layer 108, the depth of the groove pattern 100 at the end portions becomes different from the depth of the groove pattern 100 at the central portion as FIG. 18 shows, and any concave portion is produced, causing reading accuracy to be lowered. The second problem is that the surface of the resist becomes flat even when the transfer mark is transferred, thereby the thickness of the resist increases at the concave portion, that is the central portion, causing the accuracy of the pattern of the transfer mark to be lowered. The third problem is that when the multi-layer interconnection is produced in the following steps in the state where dishing has occurred, the concave portion caused by dishing remains, and various process-related problems caused by dishing may occur.
On the other hand, there is another prior art in which no underlying metal film 106 is provided as FIG. 23 shows (the third prior art). FIG. 23 is a top view of an element for illustrating a transfer mark of the third prior art, and FIG. 24 is a sectional view of the element structure along the line E-F of FIG. 23. Although the above-described problem of dishing can be avoided when no underlying metal film 106 is provided as FIG. 23 shows, the depth H of the groove pattern 100 (see FIG. 24) varies on the surface of a wafer, or between wafers, and the transfer mark cannot be read stably, arising the problem that the accuracy of alignment is not stabilized.
In order to solve the above-described problems, the object of the present invention is to avoid the effect of dishing when the groove pattern for multi-interconnection is formed; to provide a transfer mark structure for the multi-layer interconnecting process for enhancing the accuracy and stability of reading the transfer mark used for transferring the resist pattern of the following step so as to align to the location of the pattern transferred in the preceding step; and to provide a method for producing a transfer mark for the multi-layer interconnecting process.
According to a first aspect of the present invention, there is provided a transfer mark structure for a multi-layer interconnecting process for avoiding an effect of dishing on formation of a groove-like pattern for a multi-layer interconnecting, and for increasing and stabilizing reading accuracy of a transfer mark used for transfer in the following step so as to align with a transfer location in the preceding step, wherein an underlying layer immediately under the transfer mark for photoengraving formed in a step of connecting interconnecting layers has the groove-like pattern.
According to a second aspect of the present invention, there is provided a transfer mark structure for a multi-layer interconnecting process for avoiding an effect of dishing on formation of a groove-like pattern for a multi-layer interconnecting, and for increasing and stabilizing reading accuracy of a transfer mark used for transfer in the following step so as to align with a transfer location in the preceding step, wherein the transfer mark for photoengraving comprises a pattern having grooves in two directions intersecting perpendicularly to each other, and a direction of grooves of the interconnecting layer comprises a pattern having grooves in two directions intersecting perpendicularly to the pattern having grooves of the transfer mark for photoengraving.
According to a third aspect of the present invention, there is provided a method for producing a transfer mark for a multi-layer interconnecting process for avoiding an effect of dishing on formation of a groove-like pattern for a multi-layer interconnecting, and for increasing and stabilizing reading accuracy of a transfer mark used for transfer in the following step so as to align with a transfer location in the preceding step, comprising the step of: forming a groove-like pattern in an underlying layer immediately under the transfer mark for photoengraving formed in a step of connecting interconnecting layers.